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PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs

https://doi.org/10.1109/LSSC.2024.3369058

Sridharan, Amitesh; Saikia, Jyotishman; Anupreetham; Zhang, Fan; Seo, Jae-Sun; Fan, Deliang (January 2024, IEEE Solid-State Circuits Letters)

We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the number of shift–accumulate operations, bringing down the overall adder hardware cost by 1.57× while maintaining 100% utilization for all supported precision. It also employs a carry save adder tree that saves 21% of adder hardware. The 28-nm prototype chip achieves a speed-up of 2.6× , 10.8× , 2.42× , and 3.22× over prior SoTA in 1bW:1bI, 1bW:4bI, 4bW:4bI, and 8bW:8bI MACs, respectively.
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FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro

https://doi.org/10.1109/ESSCIRC59616.2023.10268770

Saikia, Jyotishman; Sridharan, Amitesh; Yeo, Injune; Venkataramanaiah, Shreyas; Fan, Deliang; Seo, Jae-Sun (September 2023, IEEE European Solid State Circuits Conference (ESSCIRC))
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity

https://doi.org/10.1109/JSSC.2023.3269148

Venkataramanaiah, Shreyas Kolala; Meng, Jian; Suh, Han-Sok; Yeo, Injune; Saikia, Jyotishman; Cherupally, Sai Kiran; Zhang, Yichi; Zhang, Zhiru; Seo, Jae-Sun (July 2023, IEEE Journal of Solid-State Circuits)

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A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification

https://doi.org/10.1109/ESSCIRC55480.2022.9911359

Venkataramanaiah, Shreyas Kolala; Meng, Jian; Suh, Han-Sok; Yeo, Injune; Saikia, Jyotishman; Cherupally, Sai Kiran; Zhang, Yichi; Zhang, Zhiru; Seo, Jae-sun (September 2022, IEEE European Solid State Circuits Conference (ESSCIRC))

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PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

https://doi.org/10.23919/VLSICircuits52068.2021.9492403

Yin, Shihui; Zhang, Bo; Kim, Minkyu; Saikia, Jyotishman; Kwon, Soonwan; Myung, Sungmeen; Kim, Hyunsoo; Joon Kim, Sang; Seok, Mingoo; Seo, Jae-sun (June 2021, 2021 Symposium on VLSI Circuits)

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K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM

https://doi.org/10.1109/ISLPED.2019.8824822

Saikia, Jyotishman; Yin, Shihui; Jiang, Zhewei; Seok, Mingoo; Seo, Jae-sun (July 2019, IEEE International Symposium on Circuits and Systems (ISCAS))

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